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MT9M001 - 1/2-inch megapixel digital image sensor features 80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_1.fm - rev. c 7/05 en 1 ?2004 micron technology, inc. all rights reserved. products and specifications disc ussed herein are subject to change by micron without notice. 1/2-inch megapixel cmos digital image sensor MT9M001c12stm (monochrome) for the latest data sheet, refer to micron?s web site: www.micron.com\imaging features ? digitalclarity ? cmos imaging technology ? array format (5:4): 1,280h x 1,024v (1,310,720 active pixels). total (incl. dark pixels): 1,312h x 1,048v (1,374,976 pixels) ? frame rate: 30 fps progressive scan; programmable ? shutter: electronic rolling shutter (ers) ? window size: sxga; programmable to any smaller format (vga, qvga, cif, qcif, etc.) ? programmable controls: gain, frame rate, frame size applications ? digital still cameras ? digital video cameras ?pc cameras general description the micron ? imaging MT9M001 is an sxga-format with a 1/2-inch cmos active-pixel digital image sen- sor. the active imaging pixel array of 1,280h x 1,024v. it incorporates sophisticated camera functions on-chip such as windowing, column and row skip mode, and snapshot mode. it is programmable through a simple two-wire serial interface. this megapixel cmos image sensor features digital- clarity?micron?s breakthrough low-noise cmos imaging technology that achieves ccd image quality (based on signal-to-noise ratio and low-light sensitiv- ity) while maintaining the inherent size, cost, and inte- gration advantages of cmos. table 1: key performance parameters the sensor can be operated in its default mode or pro- grammed by the user for frame size, exposure, gain set- ting, and other parameters. the default mode outputs an sxga-size image at 30 fr ames per second (fps). an on-chip analog-to-digital converter (adc) provides 10 bits per pixel. frame_vali d and line_valid signals are output on dedicated pins, along with a pixel clock that is synchronous with valid data. ordering information parameter typical value optical format 1/2-inch (5:4) active imager size 6.66mm(h) x 5.32mm(v) active pixels 1,280h x 1,024v pixel size 5.2m x 5.2m shutter type electronic rolling shutter (ers) maximum data rate/ master clock 48 mps/48 mhz frame rate sxga (1280 x 1024) 30 fps progressive scan; programmable adc resolution 10-bit, on-chip responsivity 2. 1 v/lux-sec dynamic range 68.2db snr max 45db supply voltage 3.0v ? 3.6v, 3.3v nominal power consumption 325mw at 3.3v; standby 275w operating temperature 0c to +70c packaging 48-pin clcc table 2: available part numbers part number description MT9M001c12stm 46-pin clcc
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001toc.fm - rev. c 7/05 en 2 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor table of contents table of contents applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 list of tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 pixel data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 pixel array structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 output data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 output data timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 frame timing formulas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 serial bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 bus idle state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 start bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 stop bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 slave address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 data bit transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 no-acknowledge bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 two-wire serial interface sample write and read seq uences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 16-bit write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 16-bit read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 feature description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 programmable gain stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 programmable analog offset stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 column and row mirror image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 column and row skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 black level calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 still image capture with external synchron ization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 line_valid signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 data output and propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 two-wire serial bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 quantum efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 image center offset and orientation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 rev c, 06/2005. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 rev b, 05/2005. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 rev a, preliminary 11/2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001lot.fm - rev. c 7/05 en 3 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor list of tables list of tables table 1: key performance parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: available part numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 3: frame timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 4: frame time?long integration time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 5: register list and default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 6: register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 7: recommended gain settings at 48 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 8: black level registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 9: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 10: ac electrical characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 11: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 12: optical area dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001lof.fm - rev.c 7/05 en 4 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor list of figures list of figures figure 1: 48-pin clcc package pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 2: block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 3: pixel array description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 4: pixel pattern detail (top right co rner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 5: spatial illustration of image re adout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 6: timing example of pixel data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 7: row timing and frame_valid/line_valid signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 8: timing diagram showing a write to reg0x09 with the va lue 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 9: timing diagram showing a read from reg0x09; returned value 0x0284 . . . . . . . . . . . . . . . . . . . . . . .12 figure 10: signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 11: readout of six columns in norm al and column mirror output mode . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 12: readout of six rows in normal and row mirror output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 13: readout of eight pixels in norm al and column skip output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14: black level calibration flow chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 15: general timing for snapshot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 16: different line_valid formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 17: data output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 18: serial host interface start condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 19: serial host interface stop condition timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 20: serial host interface data timing for write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 21: serial host interface data timing for read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 22: acknowledge signal timing after an 8-bit write to th e sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 23: acknowledge signal timing after an 8-bit read from the sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 24: quantum efficiency?mon ochrome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 25: image center offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 26: optical orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 27: 48-pin clcc package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 5 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor general description general description figure 1: 48-pin clcc package pinout diagram figure 2: block diagram 1 2 3 4 5 6 48 47 4 6 45 44 43 19 20 21 22 23 24 25 2 6 27 28 29 30 7 8 9 10 11 12 13 14 15 1 6 17 18 42 41 40 39 38 37 3 6 35 34 33 32 31 s tandby tri gg er n c re s et# n c n c oe# n c a g nd v aa a g nd a g nd n c frame_valid line_valid s trobe d g nd v dd d out <9> d out <8> d out <7> d out < 6 > d out <5> pix c lk n c v aa a g nd v dd d g nd d out <0> d out <1> d out <2> d out <3> d out <4> c lkin n c n c d g nd v dd n c n c vaapix a g nd a g nd sc lk s data n c d g nd c lo c k two-wire serial input/output 10- b it data s yn c s i g nals c ontrol re g ister analo g pro c essin g a c tive-pixel s ensor (ap s ) array s x g a 1,280h x 1,024v timin g an d c ontrol ad c
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 6 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor general description table 2: pin descriptions pin numbers symbol type description 29 clkin input clock in. master clock into sensor (48 mhz maximum). 13 oe# input output enable. oe# when high places outputs d out <0:9>, frame_valid, line_val id, pixclk, and strobe into a tri-state configuration. 10 reset# input reset. activates (low) asynchronous reset of sensor. all registers assume factory defaults. 46 sclk input serial clock. clock for serial interface. 7 standby input standby. activates (high) standby mo de, disables analog bias circuitry for power saving mode. 8 trigger input trigger. activates (hig h) snapshot sequence. 45 s data input/output serial data. serial data bus, requires 1.5 k resistor to 3.3v for pull-up. 24?28, 32?36 d out <0?9> output data out. pixel data output bits 0:9, d out <9> (msb), d out <0> (lsb). 41 frame_valid output frame valid. output is pulsed high during frame of valid pixel data. 40 line_valid output line valid. output is pulsed high du ring line of selectable valid pixel data (see reg0x20 for options). 31 pixclk output pixel clock. pixel data outputs are valid during falling edge of this clock. frequency = (master clock). 39 strobe output strobe. output is pulsed high to indicate sensor reset operation of pixel array has completed. 15,17,18,21, 47, 48 a gnd supply analog ground. provide isolated ground for analog block and pixel array. 5,23,38,43 d gnd supply digital ground. provide isolated ground for digital block. 16,20 v aa supply analog power. provide power supply for analog block, 3.3v 0.3v. 1 vaapix supply analog pixel power. provide power s upply for pixel array, 3.3v 0.3v (3.3v). 4,22,37 v dd supply digital power. provide power supply for digital block, 3.3v 0.3v. 2,3,6,9,11,12, 14,19,30,42,44 nc ? no connect. these pins must be left unconnected.
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 7 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor pixel data format pixel data format pixel array structure the MT9M001 pixel array is configured as 1,312 columns by 1,048 rows (shown in figure 3). the first 16 columns and the first ei ght rows of pixels are optically black, and can be used to monitor the black level. the la st seven columns and the last seven rows of pixels are also optically black. the black row data is used internally for the automatic black level adjustment. however, the black rows can also be read out by setting the sen- sor to raw data output mode (reg0x20, bit 11 = 1). there are 1,289 columns by 1,033 rows of optically active pixels, which provides a four-pixel boundary around the sxga (1,280 x 1,024) image. figure 3: pixel array description figure 4: pixel pattern detail (top right corner) output data format the MT9M001 image data is read out in a progressive scan. valid image data is sur- rounded by horizontal blanking and vertical blanking, as shown in figure 5. the amount of horizontal blanking and vertical blan king is programmable through reg0x05 and reg0x06, respectively. line_valid is high during the shaded region of the figure. frame_valid timing is described in ?output data timing? on page 8. (1311, 1047) 16 black columns 7 black rows 8 black rows (0, 0) 7 black columns sxga (1,280 x 1,024) + 4 pixel boundary + additional active column + additional active row = 1,289 x 1,033 active pixels pixel (8, 16) black pixels column readout direction . . . ... row readout direction ee oe ee oe ee oe eo oo eo oo eo oo ee oe ee oe ee oe eo oo eo oo eo oo ee oe ee oe ee oe eo oo eo oo eo oo ee oe ee oe ee oe
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 8 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor pixel data format figure 5: spatial illust ration of image readout output data timing the data output of the MT9M001 is synchronized with the pixclk output. when line_valid is high, one 10-bit pixel datum is output every pixclk period. figure 6: timing example of pixel data the rising edges of the pixclk signal are nominally timed to occur on the rising d out edges. this allows pixclk to be used as a clock to latch the data. d out data is valid on the falling edge of pixclk. the pixclk is high while master clock is high and then low while master clock is low. it is continuously enabled, even during the blanking period. the parameters p1, a p2, and q in figure 7 are defined in table 3. figure 7: row timi ng and frame_valid/ line_valid signals p 0,0 p 0,1 p 0,2 .....................................p 0,n-1 p 0,n p 1,0 p 1,1 p 1,2 .....................................p 1,n-1 p 1,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 p m-1,0 p m-1,1 .....................................p m-1,n-1 p m-1,n p m,0 p m,1 .....................................p m,n-1 p m,n 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 .................. 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 00 00 00 ..................................... 00 00 00 valid image horizontal blanking vertical blanking vertical/horizontal blanking line_valid pixclk d out 9-d out 0 . . . . . . . . . . . . . . . . p 0 (9:0) p 1 (9:0) p2 (9:0) p 3 (9:0) p 4 (9:0) p n-1 (9:0) p n (9:0) valid image data blanking blanking p1 a q a q ap2 . . . . . . . . . number of master clocks frame_valid line_valid
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 9 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor pixel data format frame timing formulas notes: 1. row skip mode should have no effect on the integration time. co lumn skip mode changes the effective value of column size (reg0x04) as follows: column skip 2 => r4eff = (int(r4 / 4) x 2) + 1 column skip 4 => r4eff = (int(r4 / 8) x 2) + 1 column skip 8 => r4eff = (int(r4 / 16) x 2) + 1 where the int() function truncates to the next lowest integer. now use r4eff in the equa- tion for row time instead of r4 2. default for reg0x05 = 9. however, sensor ignores any value for reg0x05 less than 19. sensor timing is shown above in terms of pixel clock and master clock cycles (please refer to figure 6). the recommended master clock frequency is 48 mhz. the vertical blank and total frame time equations assume that the number of in tegration rows (bits 13 through 0 of reg0x09) is less than the numb er of active plus blanking rows (reg0x03 + 1 + reg0x06 + 1). if this is not the case, the number of integration rows must be used instead to determine the frame time, as shown in table 4. table 3: frame timing parameter name equation (master clock) default timing notes a active data time (reg0x04 + 1) 1,280 pixel clocks = 26.7s 1 p 1 frame start blanking (242) 242 pixel clocks = 5.04s p 2 frame end blanking (2 + reg0x05 - 19) (min reg0x05 value = 19) 2 pixel clocks = 0.042s 2 q = p 1 + p 2 horizontal blanking (244 + reg0x05 - 19) (min reg0x05 value = 19) 244 pixel clocks = 5.08s 2 a + q row time ((reg0x04 + 1) + (244 + reg0x05 - 19)) 1,524 pixel clocks = 31.75s v vertical blanking (reg0x06 + 1) x (a + q) (min reg0x06 value = 15) 39,624 pixel clocks = 825.5s n rows x (a + q) frame valid time (reg0x03 + 1) x (a + q) 1,560,576 pixel clocks = 32.51ms f total frame time (reg0x03 + 1 + reg0x06 + 1) x (a + q) 1,600,200 pixel clocks = 33.34ms table 4: frame time ? long integration time parameter name equation (master clock) default timing v? vertical blanking (long integration time) (reg0 x09 ? reg0x03) x (a + q) 39,624 pixel clocks = 82.5s f? total frame time (long integration time) (reg0x09 + 1) x (a + q) 1,600,200 pixel clocks = 33.34ms
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 10 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor serial bus description serial bus description registers are written to and read from the MT9M001 through the two-wire serial inter- face bus. the sensor is a two-wire serial in terface slave and is controlled by the serial clock (sclk), which is driven by the serial interface master. data is transferred into and out of the MT9M001 through the serial data (s data ) line. the s data line is pulled up to 3.3v off-chip by a 1.5k resistor. either the slave or master device can pull the s data line down?the serial interface protocol determines which device is allowed to pull the s data line down at any given time. protocol the two-wire serial interface defines several different transmission codes, as follows: ?a start bit ? the slave device eight-bit address ? a(an) (no) acknowledge bit ? an 8-bit message ?a stop bit sequence a typical read or write sequence begins by th e master sending a start bit. after the start bit, the master sends the slave device's eigh t-bit address. the last bit of the address determines if the request will be a read or a write, where a ?0? indicates a write and a ?1? indicates a read. the slave device acknowledges its address by sending an acknowledge bit back to the master. if the request was a write, the master then transfers the 8-bit register address to which a write should take place. the sl ave sends an acknowledge bit to indicate that the register address has been received. the master then tr ansfers the data eight bits at a time, with the slave sending an acknowledge bit after each eight bits. the MT9M001 uses 16-bit data for its internal registers, thus requiring two 8-bit transfers to write to one register. after 16 bits are transferred, the register ad dress is automatically incremented, so that the next 16 bits are written to the next regi ster address. the master stops writing by sending a start or stop bit. a typical read sequence is executed as follows. first the master sends the write-mode slave address and 8-bit register address, just as in the write request. the master then sends a start bit and the read-mode slave address. the master then clocks out the regis- ter data eight bits at a time. the master se nds an acknowledge bit after each 8-bit trans- fer. the register address is auto-incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. bus idle state the bus is idle when both the data and cloc k lines are high. control of the bus is initi- ated with a start bit, and the bus is released with a stop bit. only the master can generate the start and stop bits. start bit the start bit is defined as a high-to-low transi tion of the data line while the clock line is high. stop bit the stop bit is defined as a low-to-high transi tion of the data line while the clock line is high.
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 11 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor serial bus description slave address the 8-bit address of a two-wire serial interfac e device consists of seven bits of address and 1 bit of direction. a ?0? (0xba) in the ls b (least significant bit) of the address indi- cates the write mode, and a ?1? (0xbb) indicates read mode. data bit transfer one data bit is transferred during each clock pulse. the serial interface clock pulse is provided by the master. the data must be stab le during the high period of the two-wire serial interface clock?it can only change wh en the serial clock is low. data is trans- ferred eight bits at a time, fo llowed by an acknowledge bit. acknowledge bit the master generates the acknowledge clock pu lse. the transmitter (which is the master when writing, or the slave when reading) re leases the data line, and the receiver indi- cates an acknowledge bit by pulling the data line low during the acknowledge clock pulse. no-acknowledge bit the no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. a no-acknowledge bit is used to terminate a read sequence.
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 12 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor two-wire serial interface sample write and read sequences two-wire serial interface sam ple write and read sequences 16-bit write sequence a typical write sequence for writing 16 bits to a register is shown in figure 8. a start bit given by the master, followed by the write address, starts the sequence. the image sensor will then give an acknowledge bit and expects the register address to come first, followed by the 16-bit data. after each eight-bit transf er, the image sensor will give an acknowl- edge bit. all 16 bits must be written before th e register will be updated. after 16 bits are transferred, the register addres s is automatically incremented so that the next 16 bits are written to the next register. the master st ops writing by sending a start or stop bit. figure 8: timing diagra m showing a write to reg0 x09 with the value 0x0284 16-bit read sequence a typical read sequence is shown in figure 9. first the master has to write the register address, as in a write sequence. then a start bit and the read address specifies that a read is about to happen from the register. the master then clocks out the register data eight bits at a time. the master sends an acknowle dge bit after each eight-bit transfer. the reg- ister address should be incremented after every 16 bits is transferred. the data transfer is stopped when the master sends a no-acknowledge bit. figure 9: timing diagra m showing a read from reg0 x09; returned value 0x0284 sclk s data start ack 0xba addr ack ack ack stop reg0x09 1000 0100 0000 0010 sclk s data start ack 0xba addr 0xbb addr 0000 0010 reg0x09 ack ack ack stop 1000 0100 nack
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 13 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor registers registers register map note: 1 = always 1 0 = always 0 d = programmable table 5: register list and default values register # (hex) description data format (binary) default value (hex) 0x00 chip version 1000 0100 0001 0001 0x8431 0x01 row start 0000 0ddd dddd dddd 0x000c 0x02 column start 0000 0ddd dddd dddd 0x0014 0x03 row size (window height ) 0000 0ddd dddd dddd 0x03ff 0x04 col size (window width) 0000 0ddd dddd dddd 0x04ff 0x05 horizontal blanking 0000 0ddd dddd dddd 0x0009 0x06 vertical blanking 0000 0ddd dddd dddd 0x0019 0x07 output control 0000 0000 0d00 00dd 0x0002 0x09 shutter width 00dd dddd dddd dddd 0x0419 0x0b restart 0000 0000 0000 000d 0x0000 0x0c shutter delay 0000 0ddd dddd dddd 0x0000 0x0d reset 0000 0000 0000 000d 0x0000 0x1e read options 1 1000 dddd 00dd dd00 0x8000 0x20 read options 2 dd01 0dd1 d00d d10d 0x1104 0x2b even row, even column 0000 0000 0ddd dddd 0x0008 0x2c odd row, even column 0000 0000 0ddd dddd 0x0008 0x2d even row, odd column 0000 0000 0ddd dddd 0x0008 0x2e odd row, odd column 0000 0000 0ddd dddd 0x0008 0x35 global gain 0000 0000 0ddd dddd 0x0008 0x5f cal threshold dddd dddd d0dd dddd 0x0904 0x60 even row, even column 0000 000d dddd dddd 0x0000 0x61 odd row, odd column 0000 000d dddd dddd 0x0000 0x62 cal ctrl d00d d100 1001 1ddd 0x0498 0x63 even row, odd column 0000 000d dddd dddd 0x0000 0x64 odd row, even column 0000 000d dddd dddd 0x0000 0xf1 chip enable 0000 0000 0000 00dd 0x0001
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 14 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor registers table 6: register description register bit description chip id 0x00 15:0 this register is read-only and gives th e chip identificati on number: 0x8431. window control these registers control th e size of the window. 0x01 10:0 first row to be read out ? default = 0x000c (12). 0x02 10:0 first column to be read out ? default = 0x0014 (20). register value must be an even number. 0x03 10:0 window height (number of rows - 1) ? default = 0x03ff (1023). minimum value for 0x03 = 0x0002. 0x04 10:0 window width (number of columns - 1) ? default = 0x04ff (1279). register value must be an odd number. minimum value for 0x04 = 0x0003. blanking control these registers control the blan king time in a row (called column fill-in or horizontal blanki ng) and between frames (vertical blanking). horizontal blanking is specified in terms of pixe l clocks. vertical blanking is specified in terms of row readout times. the actual imager timing can be calculated using table 3, frame timing, on page 9. 0x05 10:0 horizontal blanking ? default = 0x0009 (9 pixels). 0x06 10:0 vertical blanking ? default = 0x0019 (25 rows). output control this register controls various featur es of the output format for the sensor. 0x07 0 synchronize changes (copied to reg0xf1, bit1). 0 = normal operation. update changes to registers that affect image brightness (integration time, integration delay, gain, horizontal blanking and vertical blanking, window size, row/column skip or row mirror) at the next frame boundary. the ?fra me boundary? is 8 row_times before the rising edge of frame_valid. (if ?show dark rows? is set, it will be coincident with the rising edge of frame_valid.) 1 = do not update any changes to these sett ings until this bit is returned to ?0.? 1 chip enable (copied to reg0xf1, bit0). 1 = normal operation. 0 = stop sensor readout. when this is returned to ?1,? sensor readout restarts at the starting row in a new frame. the digital power consumption can then also be reduced to less than 5ua by turning off the master clock. 2 reserved ? default is 0; set to zero at all times. 3 reserved ? default is 0; set to zero at all times. 6 use test data. when set, a test pattern will be output instead of the sampled image from the sensor array. the value sent to the d out [9:0] pins will alternate between the te st data register (reg0x32) in even columns and the inverse of the test data register for odd columns. the outp ut ?image? will have the same width, height, a nd frame rate as it would otherwise ha ve. no digital processing (gain or offset) is applied to the data. when clear (the de fault), sampled pixel valu es are output normally.
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 15 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor registers pixel integration control these registers (along with the window sizing and blanking registers) control the integration time for the pixels. the actual total in tegration time ( t int) is: t int = reg0x09 x row time - overh ead time - reset delay, where: row time = ((reg0x04 + 1) + 244 + reg0x05 - 19) pixel clock periods overhead time = 180 pixel clock periods reset delay = 4 x reg0x0 c pixel clock periods if the value in reg0x0c exceeds (row time - 548)/4 pixel clock cy cles, the row time will be extended by (4 x reg0x0c - (row time - 548)) pixel clock cycles. in this expression, the row time term, reg0x09 x ((number of columns) + 244 + horizont al blanking register - 19), corresponds to the number of rows inte grated. the overhead time (180 pixel cloc ks) is the overhead time between the read cycle and the reset cycle, and the final term is the effect of the reset delay. typically, the value of reg0x09 is limited to the number of rows per frame (which includes vertical blanking rows) such that the frame rate is not affected by the integration time. if reg0 x09 is increased beyond the total number of rows per frame, the MT9M001 will add addi tional blanking rows as needed . a second constraint is that t int must be adjusted to avoid banding in the image from light fl icker. under 60hz flicker, this means t int must be a multiple of 1/120 of a second. under 50hz flicker, t int must be a multiple of 1/100 of a second. 0x09 13:0 number of rows of integration ? default = 0x0419 (1049). 0x0c 10:0 shutter delay ? default = 0x0000 (0). this is the number of master clocks times four that the timing and control logic waits before as serting the reset for a given row. frame restart 0x0b 0 setting bit 0 to ?1? of reg0x0b wi ll cause the sensor to abandon the readout of the current frame and restart from the first row. this register auto matically resets itself to 0x0000 after the frame restart. the first frame after this event is consid ered to be a "bad frame" (see description for reg0x20, bit0). reset 0x0d 0 this register is used to reset the sensor to its de fault, power-up state. to put the MT9M001 in reset mode first write a ?1? into bit 0 of this register, then write a ?0? into bit 0 to resume operation. table 6: register description (continued) register bit description
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 16 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor registers read mode 1 in read mode 1, this register is used to cont rol many aspects of the readout of the sensor. 0x1e 0 reserved ? default is 0; set to zero at all times. 1 reserved ? default is 0; set to zero at all times. 2 column skip 4 ? default is 0 (disable). 1 = enable. 3 row skip 4 ? default is 0 (disable). 1 = enable. 4 column skip 8 ? default is 0 (disable). 1 = enable. 5 row skip 8 ? default is 0 (disable). 1 = enable. 6 reserved ? default is 0; do not change. 7 reserved ? default is 0; do not change. 8 snapshot mode ? default is 0 (continuous mode). 1 = enable (wait for tri gger; trigger can come from outside signal (trigger pin on the sensor) or from serial interface register restart, i.e. programming a ?1? to bit 0 of reg0x0b. 9 strobe enable ? default is 0 (no strobe signal). 1 = enable strobe (signal output from the sensor during the time all rows are integrating. see strobe width for more information). 10 strobe width ? default is 0 (strobe signal width at mi nimum length, 1 row of integration time, prior to line valid going high). 1 = extend strobe width (strobe signal width extends to entire time all rows are integrating). 11 strobe override ? default is 0 (strobe signal created by digital logic). 1 = override strobe signal (strobe signal is set hi gh when this bit is set, low when this bit is set low. it is assumed that strobe enable is se t to ?0? if strobe override is being used). 12 reserved ? default is 0; do not change. 13 reserved ? default is 0; do not change. 14 reserved ? default is 0; do not change. 15 reserved ? default is 1; do not change. gain settings the gain is individually controllable for each of the four groups of pixels that lie in odd rows and columns, even rows and columns, odd rows and even columns, and even rows and odd columns. this is shown in the register chart. formula for ga in setting: gain 8 gain = (bit[6] + 1) x (bit[5-0] x 0.125) gain > 8 (bit[6] = 1 and bit[5] = 1) gain = 8.0 + bit[2-0] since bit[6] of the gain regist ers are multiplicative factors for the gain sett ings, there are alternat ive ways of achieving certain gains. some settings offer superi or noise performance to others, despite th e same overall gain. the following lists the recommended gain settings: gain increments recommended settings 1.000 to 4.000 0.125 0x08 to 0x20 4.25 to 8.00 0.25 0x51 to 0x60 9.0 to 15.0 1.0 0x61 to 0x67 0x2b 6:0 even row, even column ? default = 0x08 (8) = 1x gain. 0x2c 6:0 odd row, even column ? default = 0x08 (8) = 1x gain. table 6: register description (continued) register bit description
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 17 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor registers 0x2d 6:0 even row, odd column ? default = 0x08 (8) = 1x gain. 0x2e 6:0 odd row, odd column ? default = 0x08 (8) = 1x gain. 0x35 6:0 global gain ? default = 0x08 (8) = 1x gain. this register ca n be used to set all four gains at once. test data 0x32 11:2 test data. the value used to produce a test pattern in ?use test data? mode (reg0x07 bit 6). read mode 2 this register is used to control many aspects of the readout of the sensor. 0x20 0 no bad frames ? 1 = output all frames (including bad frames). 0 (default) = only output good frames. a bad frame is defined as the first frame following a change to: window size or position, horizontal blanking, row or column skip, or mirroring. 1 reserved ? default is 0; do not change. 2 reserved ? default is 1; set to ?1? at all times. 3 column skip ? 1= read out two columns, and then skip two columns (for ex ample, col 0, col 1, col 4, col 5?). 0 = normal readout (default). 4 row skip ? 1 = read out two rows, and then skip two rows (for example, row 0, row 1, row 4, row 5?). 0 = normal readout (default). 5 reserved ? default is 0; do not change. 6 reserved ? default is 0; set to zero at all times. 7 flip row ? 1 = readout starting 1 row later (alternate color pair). 0 (default) = normal readout. 8 reserved ? default is 1; set to ?1? at all times. 9 1 = "continuous" line_valid (continue producing line_valid during vertical blanking). 0 = normal line_valid (default, no line_valid during vertical blanking). 10 1 = line_valid = "c ontinuous" line_valid xor frame_valid. 0 = line_valid determined by bit 9. 11 reserved ? default is 0; do not change. 12 reserved ? default is 1; do not change. 13 reserved ? default is 0; do not change. 14 reserved ? default is 0; do not change. 15 mirror row ? 1 = read out from bottom to top (upside down). 0 (default) = normal readout (top to bottom). test data 0x32 11:2 test data. the value used to produce a test pattern in ?use test data? mode (reg0x07 bit 6). black level calibration these registers are used in the black le vel calibration. their functionality is described in detail in the next section. table 6: register description (continued) register bit description
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 18 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor registers 0x5f 5:0 thres_lo ? lower threshold for bl ack level in adc lsbs ?d efault = 000100. 7 1 = override automatic thres_hi and thres_lo adjust (thres_hi always = bits 14:8; thres_lo always = bits 5:0). default = 0 = automatic thres_ hi and thres_lo adjustment. 14:8 thres_hi ? maximum allowed black level in adc lsbs (default = thres_lo + 5). black level maximum is set to this value when bit 7 = 1; black level maximum is reset to this value after every black level average restart if bit 15 = 1 and bit 7 = 0. 15 no gain dependence. 1 = thres_lo is set by the programmed value of bits 5:0, thres_hi is reset to the programmed value (bits 14:8) after every black level average restart. 0 = thres_lo and thres_hi are set automatically, as described above. 0x60 8:0 even row, even column ? analog offset correction value for even row, even column, bits 0:7 sets magnitude, bit 8 set sign. 0 = positive; 1 = negative. two?s complement, if bit 8 = 1, offset = bits [0:7] - 256. 0x61 8:0 odd row, odd column ? analog offset correction value for odd row, odd colu mn, bits 0:7 sets magnitude, bit 8 set sign. 0 = positive; 1 = negative. two?s complement, if bit 8 = 1, offset = bits [0:7] - 256. 0x62 0 manual override of black level correction. 1 = override automatic black level correction with programmed values. 0 = normal operation (default). 2:1 force/disable black level calibration. 00 = apply black level calibration du ring adc operation only (default). 10 = apply black level calibration continuously. x1= disable black level correction (o ffset correction voltage = 0.0v). (in this case, no black leve l correction is possible). 4:3 reserved ? default is 1; do not change. 6:5 reserved ? default is 0; do not change. 7 reserved ? default is 1; do not change. 9:8 reserved ? default is 0; do not change. 10 reserved ? default is 1; do not change. 11 1 = do not reset the upper threshold af ter a black level recalculation sweep. 0 = reset the upper threshold after a bl ack level recalculation sweep (default). 12 1 = start a new running digitally filtered average fo r the black level (this is internally reset to ?0? immediately), and do a rapid sweep to find the new starting point. 0 = normal operation (default). 14:3 reserved ? default is 0; set to zero at all times. 15 1 = do not perform the rapid black level sweep on new gain settings. 0 = normal operation. 0x63 8:0 even row, odd column ? analog offset correction value for even row, odd column, bits 0:7 sets magnitude, bit 8 set sign. 0 = positive; 1 = negative. two?s complement, if bit 8 = 1, offset = bits [0:7] - 256. 0x64 8:0 odd row, even column ? analog offset correction value for odd row, even column, bits 0:7 sets magnitude, bit 8 set sign. 0 = positive; 1 = negative. two?s complement, if bit 8 = 1, offset = bits [0:7] - 256. table 6: register description (continued) register bit description
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 19 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor registers chip enable and two-wire serial interface write synchronize. 0xf1 0 mirrors the functionali ty of reg0x07 bit1 (chip enable). 1 = normal operation. 0 = stop sensor readout; when th is is returned to ?1,? sensor re adout restarts at the starting row in a new frame. table 6: register description (continued) register bit description
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 20 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor feature description feature description signal path the MT9M001 signal path consists of two st ages, a programmable gain stage and a pro- grammable analog offset stage. programmable gain stage a total programmable gain of 15 is available and can be calculated using the following formula: gain 1 to 8: gain = (bit[6] + 1) x (bit[5:0] x 0.125) for gain higher than eight, the user would need to set bit[6:5] = 11 and use the lower 3 lsb's bit[2:0] to set the higher gain values. the formula for obtaining gain greater than eight is as follows: total gain = 8 + bit[2:0] for example, for total gain = 12, the value to program is bit[6?0] = 1100100. the maximum total gain = 15, i.e. bit[6:0] = 1100111. the gain circuitry in the MT9M001 is designed to offer signal gains from one to 15. the minimum gain of one corresponds to the lowest setting where the pixel signal is guaran- teed to saturate the adc unde r all specified operating conditions. any reduction of the gain below this value may cause the sensor to saturate at adc output values less than the maximum, under certain conditions. it is recommended that this guideline be fol- lowed at all times. since bit[6] of the gain registers are multipli cative factors for the gain settings, there are alternative ways of achieving certain gains. some settings offer superior noise perfor- mance to others, despite the same overall gain. recommended gain settings are listed in tabl e 7. figure 10: signal path table 7: recommended gain settings at 48 mhz nominal gain increments recommended settings 1 to 4.000 0.125 0x08 to 0x20 4.25 to 8.00 0.25 0x51 to 0x60 9 to 15 1.0 0x61 to 0x67 x + pixel output (signal minus reset) offset correction voltage (reg0x60, reg0x61, reg0x63, reg0x64) (signed lower 9 bits) x 2mv 10-bit adc adc data (9:0) gain selection (reg0x2b - 0x2e)
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 21 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor feature description programmable analog offset stage the programmable analog offset stage corrects for analog offset that might be present in the analog signal. the user would need to program register 0x62 appropriately to enable the analog offset correction. the lower eight bits (bit[7:0]) determines the absolute value of the analog offset to be corrected and bit[8] determines the sign of the correction. when bit[8] is ?1?, the sign of the correction is negative and vice versa. th e analog value of the correction relative to the analog gain stage can be dete rmined from the following formula: analog offset (bit[8] = 0) = bit[7:0] x 2mv analog offset (bit[8] = 1) = - (bit[7:0] x 2mv) column and row mirror image by setting bit 14 of reg0x20, the readout order of the columns will be reversed, as shown in figure 11. figure 11: readout of si x columns in normal and co lumn mirror output mode by setting bits 15 of reg0x20 the readout orde r of the rows will be reversed, as shown in figure 12. figure 12: readout of six rows in normal and row mirror output mode column and row skip by setting bit 3 of reg0x20, only half of the columns set will be read out. an example is shown in figure 13. only columns with bit 1 equal to ?0? will be read out (xxxxxxx0x). the row skip works in the same way and will on ly read out rows with bit 1 equal to ?0.? row skip mode is enabled by setting bit 4 of reg0x20. for both row and column skips, the number of rows or columns read out will be half of what is set in reg0x03 or reg0x04, respectively. d out 9?d out 0 line_valid normal readout col0 (9:0) col1 (9:0) col2 (9:0) col3 (9:0) col4 (9:0) col5 (9:0) d out 9?d out 0 reverse readout col5 (9:0) col4 (9:0) col3 (9:0) col2 (9:0) col1 (9:0) col0 (9:0) d out 9?d out 0 frame_valid normal readout row0 (9:0) row1 (9:0) row2 (9:0) row3 (9:0) row4 (9:0) row5 (9:0) d out 9?d out 0 reverse readout row4 (9:0) row5 (9:0) row3 (9:0) row2 (9:0) row1 (9:0) row0 (9:0)
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 22 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor feature description figure 13: readout of eight pixels in normal and column skip output mode black level calibration the MT9M001 has automatic black level calibr ation on-chip which can be overridden by the user, as described below and shown in figure 14. the automatic black level calibration measures the average value of 256 pixels from two dark rows of the chip for each of the four co lors. the pixels are averaged as if they were light-sensitive and passed through the appropri ate color gain. this average is then digi- tally filtered over many frames. for each color, the new filtered average is compared to a minimum acceptable level (to screen for too low a black level) and a maximu m acceptable level. if the average is lower than the minimum acceptable level, the offs et correction voltage for that color is increased by one offset lsb (offset lsbs do not match adc lsbs; typically, one offset lsb is approximately 2mv). if it is above the maximum level, the level is decreased by 1 lsb (2mv). the upper threshold is automa tically adjusted upwards whenever an upward shift in the black level from below the minimum results in a new black level above the maximum. this prevents black level oscillation from below the minimum to above the maximum. the lower threshold is increased with the maximum gain setting according to the formula described under reg0x5f. this prevents clipping of the black level. whenever the gain or any of the readout timi ng registers is changed (shutter width, ver- tical blanking, number of rows or columns, or the shutter delay) or if the black level recalculation bit, reset bit or restart bit is set, the running digitally filtered average is reset to the first average of the dark pixels. th e digital filtering over many frames is then restarted. whenever the gain or the readout timing registers are changed, the upper threshold is restored to its default value. after changes to the sensor configuration, la rge shifts in the black level calibration can result. to quickly adapt to this shift, a rapi d sweep of the black level during the dark-row readout is performed on the first frame after certain changes to the sensor registers. any changes to the registers listed above will ca use this recalculation. the data from this sweep allows the sensor to choose an accurate new starting point for the running aver- age. this procedure can be disabled as described under reg0x5f. figure 14: black level calibration flow chart d out 9?d out 0 line_valid normal readout g0 (9:0) r0 (9:0) g1 (9:0) r1 (9:0) g2 (9:0) r2 (9:0) g3 (9:0) r3 (9:0) d out 9?d out 0 line_valid column skip readout g0 (9:0) r0 (9:0) g2 (9:0) r2 (9:0) x + pixel output (signal minus reset) offset correction voltage (color-wise) 10-bit adc adc data (9:0) gain selection (color-wise)
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 23 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor registers registers table 8: black level registers register bit description reg0x5f this register controls the operation of the black level calibration thresholds. 15 no gain dependence. 1 = thres_lo is set by the programmed value of bits 5:0, thres_hi is reset to the programmed value (bits 14:8) after every black level average restart. 0 = thres_lo and thres_hi are set automatically as described below. 14:8 thres_hi ? maximum allowed black level in adc lsbs (default = thres_lo + 5). black level maximum is set to this value when bit 7 = 1, black level maximum is reset to this value after every black level average restart if bit 15 = 1 and bit 7 = 0. 7 1 = override automatic thres_hi an d thres_lo adjust (thres_hi always = bits 14:8, thres_lo always = bits 5:0). 0 = automatic thres_hi and thres_lo adjustment. 5:0 thres_lo ? lower threshold for black level in adc lsbs. under default automatic opera tion (bit 7 = 0, bit 15 = 0), thres_lo = reggain max /4 x (reggain max , bit 6 +1) x (reggain max , bit 7 +1), where reggain max is the maximum of the four independent gain register settings. whenever a jump in the calibratio n causes the black level data to change from below thres_lo to above thres_hi, thres_hi is adjusted according to the following: if new black level < 64: thres_hi = thres_lo + 2 + (2 x delta), where delta = new black level - thres_lo if new black level > 63 and < 119 : thres_hi = new black level + 4 if new black level > 119: thres_hi = 123 after any recalculation of the black level and averag e restart, thres_hi is rese t to either thres_lo + 5 (automatic, default mode), th res_hi (bit 7 = 1). reg0x62, bit 11 will override this. reg0x62 this register is used to control the au tomatic black level ca libration circuitry. 15 1 = do not perform the rapid black level sweep on ne w gain settings. 0 = normal operation. 14 reserved ? default is 0; do not change. 13 reserved ? default is 0; do not change. 12 1 = start a new running digitally filtered average for the black level (this is internally reset to ?0? immediately), and do a rapid sweep to find the ne w starting point. 11 1 = do not reset the upper threshold a fter a black level recalculation sweep. 0 = reset the upper threshold after a bl ack level recalculation sweep (default). 10:3 reserved ? default is 1; do not change. 2:1 force/disable black level calibration. 00 = apply black level calibration during adc operation only (default). 10 = apply black level calibration continuously. x1 = disable black level correction (offset correction voltage = s kew voltage = 0.0v). (in this case, no black level correction is possible). 0 manual override of black level correction. 1 = override automatic black level correction with programmed values. 0 = normal operation (default).
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 24 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor registers reg0x60, reg0x61, reg0x63, reg0x64 these registers contain the 9-bit signed black leve l calibration values. in normal operation, these values are calculated at the beginn ing of each frame. however, if re g0x62, bit 0 is set to ?1,? these registers can be written to, over riding the automatic black level ca lculation. this feature can be used in conjunction with readout of the black rows (reg0x20, bit 11) if the user would like to use an external black level calibration circuit. the of fset correction voltage is generated according to the following formula: offset correction voltage = (9-bit signed calibration value, -256 to 255) x (2mv x enable bit) two?s complement, if bit 8 = 1, offset = bits [0:7] - 256 adc input voltage = pixel output voltage x analog gain - offset correction voltage registers table 8: black level registers (continued) register bit description
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 25 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor registers still image capture with external synchronization in continuous mode video image capture, th e trigger signal should be held low or ?0.? to capture a still image, the sensor mu st first be put into snapshot mode by pro- gramming a ?1? in register 0x1e, bit 8. in sn apshot mode, the sensor waits for a trigger signal (frame_valid, line_valid signals are low, pixel clock signal continues). when the trigger signal is received (active high), one frame is read out (a trigger signal can also be achieved by programming a restart?for example, program a ?1? to bit 0 of reg0x0b). the reset, readout timing for th at frame will be the same as for a continu- ous frame with similar register settings; the only difference is that only one frame is read out. general timing for the snapshot mode is shown in figure 15. figure 15: general timing for snapshot mode line_valid signal by setting bit 9 and 10 of reg0x20 the line va lid signal can get three different output for- mats. the formats are shown when reading out four rows and two vertical blanking rows (figure 16). in the last format, the line_valid signal is the xor between the continu- ously line_valid signal and the frame_valid signal. figure 16: different line_valid formats trigger reset row 1 reset row reset row x strobe readout max strobe length (all rows integrating) min strobe length (1 row time) default frame_valid line_valid continuously frame_valid line_valid xor frame_valid line_valid
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 26 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor electrical specifications electrical specifications data output and propagation delays by default, the MT9M001 launches pixel da ta, frame_valid and line_valid with the rising edge of pixclk. the expectat ion is that the user captures d out [7:0], frame_valid and line_valid using the rising edge of pixclk. figure 17: data output timing diagram table 9: dc electrical characteristics (dc setup conditions: f clkin = 48 mhz, v dd = 3.3v, v aa = 3.3v, vaapix = 3.3v, t a = 25c) symbol definition condition min typ max units v dd core digital voltage 33.3 3.6 v v aa analog voltage 33.3 3.6 v vaapix pixel supply voltage 33.3 3.6 v v ih input high voltage v pwr - 0.3 v pwr + 0.3 v v il input low voltage -0.3 0.8 v i in input leakage current no pull-up resistor; v in = v dd or d gnd -15 15 a v oh output high voltage v pwr - 0.2 ? v v ol output low voltage 0.2 v i oz tri-state output leakage current ?15a i dd digital operating current ?20 24ma i aa analog operating current ?85 110ma i aapix pixel supply current ?5 10ma c lkin pix c lk t r t f t c lkin data[0-7] frame vali d / line vali d xxx xxx xxx xxx xxx xxx note: frame_vali d lea d s line_vali d b y 242 pix c lks. note: frame_vali d trails line_vali d (1+ re g 0x05-19) pix c lk s . t c p t pfl t pll t fv s t pd t oh p 0 p 1 p 2 p n t lv s t o s t pfh t plh t
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 27 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor electrical specifications . note: 1 stresses greater than those listed may cause permanent damage to th e device. this is a stress rating only, and fu nctional operation of the device at these or any other conditions above those indicated in the operational sections of this sp ecification is not implied. expo- sure to absolute maximum rati ng conditions for extended periods may affect reliability. i stdbyd digital standby current stdby = v dd , clkin = 0 mhz ?9 20ma i stdbyd w /clk digital standby current stdby = v dd , clkin = 48 mhz ?55 125a i stdbyda analog standby current stdby = v dd ?80 100a table 10: ac electrical characteristics (ac setup conditions: f clkin= 48 mhz, v dd = 3.3v, v aa = 3.3v, vaapix = 3.3v, output load = 30pf, t a = 25c)) symbol definition condition min typ max unit f clkiin input clock frequency 1?48mhz t clkin input clock period 1000 ? 20.83 ns t pixclk period 1000 ? 20.83 ns t r input clock rise time 4v/ns t f input clock fall time ?4 v/ns clock duty cycle 45/55 50/50 55/45 % t cp clkin to pixclk propagation delay ?10? ns t pd pixclk to data valid ??1 ns t pfh pixclk to fv high ??7 ns t plh pixclk to lv high ??7 ns t pfl pixclk to fv low ??3 ns t pll pixclk to lv low ??2 ns t os setup time for data befo re falling edge of pixclk t/2 -1 t/2 t/2 +1 ns t oh hold time for data after falling edge of pixclk t/2 -1 t/2 t/2 +1 ns t fvs setup time for fv befo re falling edge of pixclk 23?ns t lvs setup time for lv befo re falling edge of pixclk 23?ns c load load capacitance 30 pf table 11: absolute maximum ratings symbol parameter rating unit min max t op operating temperature 070c t stg 1 storage temperature ?40 125 c table 9: dc electrical characteristics (continued) (dc setup conditions: f clkin = 48 mhz, v dd = 3.3v, v aa = 3.3v, vaapix = 3.3v, t a = 25c) symbol definition condition min typ max units
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 28 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor electrical specifications two-wire serial bus timing the two-wire serial bus operation requir es certain minimum master clock cycles between transitions. these are specified in the following diagrams in master clock cycles. figure 18: serial host inte rface start co ndition timing figure 19: serial host interface stop condition timing note: all timing are in un its of master clock cycle. figure 20: serial host interface data timing for write note: s data is driven by an off-chip transmitter. figure 21: serial host interface data timing for read note: s data is pulled low by the sensor, or allowed to be pulled high by a pull-up resistor off- chip. sclk 5 s data 4 sclk 5 s data 4 sclk 4 s data 4 sclk 5 s data
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 29 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor electrical specifications figure 22: acknowledge si gnal timing after an 8- bit write to the sensor figure 23: acknowledge si gnal timing after an 8- bit read from the sensor note: after a read, the master receiver must pull down s data to acknowledge receipt of data bits. when read sequence is complete, the master must generate a no acknowledge by leaving s data to float high. on the following cycle, a start or stop bit may be used. quantum efficiency figure 24: quantum efficiency?monochrome sclk sensor pulls down s data pin 6 s data 3 sclk sensor tri-states s data pin (turns off pull down) 7 s data 6 0 10 20 30 40 50 60 350 450 550 650 750 850 950 1050 quantum efficiency (%) wavelength (nm) quantum efficiency - monochrome
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 30 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor electrical specifications image center offset and orientation figure 25: image center offset notes: 1. x and y coordinates referenced to center of die. 2. die center = package center. 3. image center offset from package center (x = 0.015mm, y = 0.712mm). figure 26: optical orientation table 12: optical area dimensions optical area pixel x-dimension y-dimension sxga center of pixel (20, 12) 3,340.70m 3,372.45m center of pixel (1299, 1035) -3,315.2m -1,952.35m chip size, mm (including seal ring) 7.75mm 7.75mm pad 1 pixel (0,0) die center image center 7.75mm pixel array 0.015mm 0.712mm pixel (12, 20) black and boundary pixels 7.75mm up pin 1 pixel array top of board bottom of board
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo are tr ademarks of micron technology, inc. all other trademarks are the prope rty of their respective owners. this data sheet contains minimum and maximum limi ts specified over the complete power supply and temperature range for production devices. although consider ed final, these specifications are subject to change, as further product development and da ta characterization sometimes occur. MT9M001 - 1/2-inch megapixel digital image sensor electrical specifications 80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 31 ?2004 micron technology, inc. all rights reserved. figure 27: 48-pin cl cc package outline drawing note: all dimensions in millimeters. seating plane 1.016 typ 1 48 11.176 lid material: borosilicate glass 0.55 thickness substrate material: alumina ceramic 11.176 5.588 7.11 47x 1.02 1.016 typ 48x 0.50 7.125 0.125 6.398 0.125 13.00 ctr 13.00 ctr 2.00 2.21 0.27 48x r 0.19 7.11 14.220 +0.300 -0.125 14.220 +0.300 -0.125 5.588 a d c b optical area optical center package and die center maximum rotation of optical area relative to package edges b and c : 1o maximum tilt of optical area relative to seating plane a : 50 microns maximum tilt of optical area relative to top of cover d : 50 microns 0.015 for reference only first clear pixel 0.712 for reference only 1.270 0.085 1 0.44 for reference only 0.94 0.26 1 lead finish: gold plating, 20 micro inches minimum thickness note: 1. these dimensions are non accumulative
80a3e031 micron technology, inc., reserves the right to change products or specifications without notice. MT9M001_ds_2.fm - rev.c 7/05 en 32 ?2004 micron technology, inc. all rights reserved. MT9M001 - 1/2-inch megapixel digital image sensor revision history revision history rev c, 06/2005 ? remove color information ? updated table 1, key performance parameters, on page 1 ? updated table 5, register list and default values, on page 13 ? updated table 6, register description, on page 14 ? updated figure 12, readout of six rows in normal and row mirror output mode, on page 21 ? deleted figure 13, readout of eight pixels in normal and column skip output mode, on page 22 ? updated table 10, ac electrical characteristics, on page 27 ? updated figure 25, image center offset, on page 30 ? updated figure 27, 48-pin clcc package outline drawing, on page 31 rev b, 05/2005 ? page 1, remove preliminary disclaimer ? page 1, add key performance parameters table, add applications ? page 2, add table of contents ? page 6, update pin description table ? page 11, update serial bus description ? page 12, update timing diagram showing a read from reg0x09; returned value 0x0284 figure ? page 13, update register list and default values table ? page 14, update register description table (add test data-reg0x32[11:2], update output control-reg0x07[6] ? page 28, update ac and dc elec trical characteristics table ? page 29, add figure 17, data output timing di agram, and absolute maximum ratings, table 11 ? page 30, update propagation delay for frame_valid and li ne_valid signals (data output and propagation delays ? page 32, delete quantum efficiency figure (color) ? page 33, update figure 27, 48-pin clcc package outline drawing rev a, preliminary 11/2003 ? initial release of document

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